Complementary metal oxide semiconductor (CMOS) technology is the primary technology employed for ultra-large scale integrated (VLSI) circuits. Over the past decades, reduction in the size of CMOS transistors has been a principle focus of the microelectronics industry.
Transistors, such as metal oxide semiconductor field-effect transistors (MOSFETs), are generally either bulk semiconductor-type devices or silicon-on-insulator (SOI)-type devices. Most integrated circuits are fabricated in a CMOS process on a bulk semiconductor substrate.
In bulk semiconductor-type devices, transistors, such as MOSFETs, are built on top of the surface of a bulk substrate. The substrate is doped to form source and drain regions, and the conductive layer is provided between the source and drain regions. The conductive layer operates as a gate for the transistor, and the gate controls current in a channel between the source and the drain regions. As transistors become smaller, the body thickness of the transistor (or thickness of the depletion layer below the inversion channel) must be scaled down to achieve superior short-channel performance.
As an enhancement on conventional, planar transistor structures, three-dimensional (3D) transistor devices are under development, including FinFET devices and nanowire devices. In a FinFET, a generally vertically-positioned, fin-shaped active area is formed, and a gate electrode encloses both the sides and upper surface of the fin-shaped active area to form a tri-gate structure.
In a nanowire structure or device, a nanowire is formed for the channel region of the device. Such nanowire devices offer one possible solution to the continuing demand for semiconductor devices with smaller feature sizes. However, enhancements to manufacturing techniques for nanowire devices are needed.